A constant-time hardware architecture for the CSIDH key-exchange protocol

Sina Bagheri; Masoud Kaveh; F. Hernando-Galego; Diego Martín; Nuria Serrano

doi:10.48550/arXiv.2508.11082

Publication record · 2025

A constant-time hardware architecture for the CSIDH key-exchange protocol

Authors: Sina Bagheri · Masoud Kaveh · F. Hernando-Galego · Diego Martín · Nuria Serrano
Year: 2025
Publisher: arXiv
Journal or publication: arXiv preprint
Google Scholar citations: 1

Research summary

A constant-time CSIDH-512 accelerator establishes hardware baselines for post-quantum key generation on FPGA and ASIC. A finite-state controller and deeply pipelined 512-bit arithmetic unit mitigate timing leakage while quantifying latency, cycle count and implementation cost.

Original description prepared for this website; consult the publication for its authoritative abstract.

DOI 10.48550/arXiv.2508.11082 ↗ · Open-access version ↗ · View Google Scholar record ↗